During initial stages of circuit design, interconnect structures or breadboards are used for circuit layout and performance testing and evaluation. Like their integrated circuit counterparts, breadboard interconnect characteristics must faithfully replicate intended electrical parameters in order to accurately test the functionality of a given circuit configuration. For this purpose a typical breadboard circuit layout may contain one or more layers of interconnect metal plated on one or both sides of an insulator board, with plated through-holes passing through the board to electrically join selected locations of an interconnect pattern to the opposite side of the board where additional pattern or ground plane conductive layers ar disposed. The patterning of the metallized conductor (usually copper) itself is originally precisely defined in accordance with preselected electrical circuit impedance parameters (in terms of line width and thickness) and is expected to be produced as such in an actual breadboard implementation. Unfortunately, however, because of the manner in which the metal is patterned and the through-holes plated to obtain a prescribed interconnect layout, the actual shapes of the interconnect lines may depart from their intended geometries and, consequently, alter the impedance parameters of the interconnect structure, such that accurate testing of the circuit design cannot be accomplished.
More particularly, conventional formation of a breadboard interconnect structure typically involves the selective masking of a layer of metal that has been formed over the entire surface of an insulator (e.g. Teflon) board to expose those areas whereat the interconnect metal pattern including plated through-holes is to be provided. After through-holes have been drilled in the exposed areas of the original metal, subsequent layers of interconnect metal and older lay-up are electrodeposited on the unmasked metal and in the through-holes, so as to define the composition of the interconnect structure. Then, the original mask is removed to expose the metal layer adjacent to the electrodeposited plate/solder layer overlying the originally unmasked metal. The now exposed metal of the original plated layer is removed by using the built-up layer as a mask, so that what is left is an interconnect pattern with plated through-holes. The problem with this technique of forming the plated through-holes prior to defining the interconnect pattern is the nonuniformity of the electrical characteristics in the interconnect pattern that have been created by variations in electroplating current density, so that the actual shape of the original metal layer underlying the electrodeposited build-up is altered (due to etch undercut), thereby modifying the impedance characteristics of the line pattern.